Today's computer systems are becoming increasingly sophisticated, permitting users to perform an ever increasing variety of computing tasks at faster and faster rates. The size of the memory and the speed at which it can be accessed bear heavily upon the overall speed of the computer system.
Generally, the principle underlying the storage of data in magnetic media (main or mass storage) is the ability to change and/or reverse the relative orientation of the magnetization of a storage data bit (i.e. the logic state of a “0” or a “1”). The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and/or reverse the magnetization of the particle. Generally speaking, the smaller the magnetic particle, the higher its coercivity.
A prior art magnetic memory cell may be a tunneling magneto-resistance memory cell (TMR), a giant magneto-resistance memory cell (GMR), or a colossal magneto-resistance memory cell (CMR). These types of magnetic memory are commonly referred to as spin valve memory cells (SVM). FIGS. 1A and 1B provide a perspective view of a typical prior art magnetic memory cell having two conductors.
As shown in prior art FIGS. 1A and 1B, a magnetic spin valve memory (SVM) cell 101 generally includes a data layer 103 which may alternatively be called a storage layer or bit layer, a reference layer 105, and an intermediate layer 107 between the data layer 103 and the reference layer 105. The data layer 103, the reference layer 105, and the intermediate layer 107 can be made from one or more layers of material. Electrical current and magnetic fields may be provided to the SVM cell 101 by an electrically conductive row conductor 109 and an electrically conductive column conductor 111. It is understood and appreciated that, as used herein, the terms row and column conductor have been selected for ease of discussion. Under appropriate circumstances these labels may be reversed and/or otherwise substituted for such titles as word line and bit line.
The single SVM cell shown in FIGS. 1A and 1B are typically combined with other substantially identical SVM cells. In a typical MRAM device, the SVM cells are arranged in a cross-point array. Parallel conductive columns (column 1, 2, 3 . . . ), also referred to as word lines, cross parallel conductive rows (row A, B, C . . . ), also referred to as bit lines. The traditional principles of column and row arrays dictate that any given row will only cross any given column once.
An SVM cell is placed at each intersecting cross-point between a row and a column. By selecting a particular row (B) and a particular column (3), any one memory cell positioned at their intersection (B, 3) can be isolated from any other memory cell in the array. Such individual indexing is not without complexities.
The data layer 103 is usually a layer of magnetic material that stores a bit of data as an orientation of magnetization M1 that may be altered in response to the application of an external magnetic field or fields. More specifically, the orientation of magnetization M1 of the data layer 103 representing the logic state can be rotated (switched) from a first orientation, 117 in FIG. 1A, representing a logic state of “0”, to a second orientation, 119 in FIG. 1B representing a logic state of “1”, and/or vice versa.
The reference layer 105 is usually a layer of magnetic material in which an orientation of magnetization M2 is “pinned”, as in fixed, in a predetermined direction, 121. The direction is predetermined and established by conventional microelectronic processing steps employed in the fabrication of the magnetic memory cell.
The data layer 103 and reference layer 105 may be thought of as stacked bar magnets, each long on an X axis 113 and short on a Y axis 115. The magnetization of each layer has a strong preference to align along the easy axis, generally the long X axis 113. The short Y axis 115 is generally the hard axis. As with traditional bar magnets, the data layer and reference layer each have magnetic dipoles—North (N) and South (S)—one at either end of the easy axis. The lines of magnetic force that surround the data layer and reference layers are three-dimensional and flow from the North to the South pole.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization M1 in the data layer 103 and M2 of the reference layer 105, 117 to 121 as shown in FIG. 1A or 119 to 121 as shown in FIG. 1B. For example, when an electrical potential bias is applied across the data layer 103 and the reference layer 105 in an SVM cell 101, electrons migrate between the data layer 103 and the reference layer 105 through the intermediate layer 107. The intermediate layer 107 is typically a thin dielectric layer, which is commonly referred to as a tunnel barrier layer. The phenomenon that cause the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling.
The logic state may be determined by measuring the resistance of the SVM cell 101. For example, if the orientation 119 of the magnetization M1 in the data layer 103 is parallel to the pinned orientation 121 of magnetization in the reference layer 105 the magnetic memory cell will be in a state of low resistance, R, see FIG. 1B. If the orientation 117 of the magnetization M1 in the data layer 103 is anti-parallel (opposite) to the pinned orientation 121 of magnetization in the reference layer 105, the magnetic memory cell will be in a state of high resistance, R+?R, see FIG. 1A. The orientation of M1 and, therefore, the logic state of the SVM cell 101 may be read by sensing the resistance of the SVM cell 101.
In an ideal setting, the orientation 117, 119 of the alterable magnetic field M1 in the data layer 103 is be either parallel or anti-parallel with respect to the set orientation 121 of magnetic field M2 of the reference layer 105. It is problematic that as both the data layer 103 and the reference layer 105 are generally made from ferromagnetic materials and are positioned in close permanent proximity to each other The pinned reference layer 105 may affect the orientation of the data layer 103. More specifically, the magnetization M2 of the reference layer 105 may generate a demagnetization field that extends from the reference layer 105 into the data layer 103.
The result of this demagnetization field from the reference layer 105 is an offset in the coercive switching field. This offset can result in asymmetry in the switching characteristics of the data layer 103 and the amount of switching field needed to switch the bit from parallel to anti-parallel state differs from the amount of switching field needed to switch the bit from anti-parallel state to parallel state. To achieve reliable switching characteristics and to simplify the read/write circuitry, it is desirable to reduce this offset to as near zero as possible.
The magneto-resistance ?R/R ratio is analogous to a signal-to-noise ratio S/N in that a higher S/N or magneto-resistance ratio results in a stronger signal that can be sensed to determine the state of the bit in the data layer. Thus, at least one disadvantage of a tunnel junction memory cell having a pinned reference layer in close and fixed proximity to the data layer is a potential reduction in the magneto-resistance ?R/R resulting from the angular displacement.
The pinned nature of the pinned reference layer is typically established with the use of anti-ferromagnetic (AFM) material in direct physical contact with a ferromagnetic (FM) material. AFM materials magnetically order below their Neel temperatures (TN), the temperature at which they become anti-ferromagnetic or anti-ferrimagnetic. The Neel temperature of AFM materials is analogous to the Curie Temperature (TC) of FM materials, the temperature above which a FM loses its ability to possess an ordered magnetic state in the absence of an external magnetic field. Generally TC of the FM is greater than TN of the AFM.
With respect to a traditional bar magnet there are two equally stable easy spin directions (each rotated 180 degrees) along the easy axis, generally the longer axis of the magnet—the shorter axis being the hard axis. Alignment in either direction requires the same energy and requires the same external field to align the spin of the atomic particles and thus the magnetic field, in either direction.
In establishing a reliable pinned field, it is desirable to establish a preferred orientation along one direction of an axis, typically the easy axis although in some situations it may be the hard axis. By growing the FM on an AFM in a magnetic field H or annealing in field H at a temperature above the Neel temperature of the AFM, the hysteresis loop (FM+AFM+H) becomes asymmetric and is shifted. In general, this shift is significantly greater than H, on the order of a couple hundred Oe. This unidirectional shift is called the exchange bias and demonstrates that there is now a preferred easy axis alignment direction.
The annealing step typically takes time, perhaps an hour or more. In the annealing step the reference layer is heated to a temperature greater than TN while a magnetic field is applied. As the reference layer is but one part of the memory being produced, the entire memory is typically subjected to temperatures ranging from about 200 to 300 degrees. As the temperature is lowered through TN, the spin of the AFM molecules at the interface between the AFM and FM layers will order and couple to the aligned FM spin. Such ordering of the AFM exerts a torque upon the FM material and results in establishing the pinned orientation of the reference layer.
As a result of such manufacturing stress, the reference layer may un-pin and lose its set orientation if the memory is later subjected to high temperatures. In addition, the characteristics of the data layer may be unknowingly affected by heat during some manufacturing processes.
The traditional process of reading the stored bit is somewhat undesirable, although effective. In general, the row conductor 109 and column conductor 111 for a given SVM cell 101 are selected by appropriate control logic. The control logic is generally further responsible for applying a sense current through the selected column conductor 111 and row conductor 109, measuring the resistance of the current through the SVM cell 101, and recording the measured resistance value. Next, a larger write current is applied to put the data layer 103 into a known orientation. Then, a sense current is re-applied and the resistance of the SVM cell 101 is measured again.
The value determined from a known orientation (the second sense) is then compared with the value from the initial condition (the first sense). The values will either be the same or different, permitting a determination of the data value. If necessary, such as where the initial position is determined to be opposite to the known orientation, a write back can be performed to restore the original initial value. This process is a self reference process and is known as double sampling—the first sample being the initial read and the second being after the known orientation write.
Multiple variations of self reference sampling may be performed with double sampling; however, the underlying negative aspect remains unchanged, namely, to determine the value stored in the data layer 103, it is necessary to change the value in the data layer 103. This change for the purpose of sensing introduces a significant element of risk in data corruption should an error occur during the repetitive sense and write operations.
As a traditional sense operation involves the re-writing the data layer 103 of the SVM cell 101, the physical design of the SVM cell 101 is typically dictated by the stresses imposed by the write process, as both the sense and write operations are performed using the same row and column conductors 109 and 111. As the write magnetic field is typically generated by current applied to the row and column conductors 109 and 111, which are in electrical contact with the SVM cell 101, it is desirable for the SVM cell 101 to be robust enough to withstand the applied current. Design and manufacturing issues are therefore generally focused upon the requirements imposed by the write operation, such as greater electrical current and magnetic fields, higher applied voltages, more robust characteristics in the power supply, row and column conductors 109 and 111 and appropriate buffering spaces.
With respect to magnetic memory components, it is well known that as size decreases, coercivity increases. A large coercivity is generally undesirable, as it must be switched using a greater magnetic field. In turn, a greater magnetic field requires a greater power source and may require larger switching transistors and conductors. Providing large power sources and large switching transistors is generally at odds with industry requirements to reduce the size of nano-scaled components.
In addition, to mitigate the possibility of inadvertently switching a neighboring memory cell, nanometer scaled memory cells are generally more widely spaced relative to their overall size than are larger, non-nanometer sized memory cells. Moreover, as the size of the magnetic memory decreases, the unused buffering space between individual memory cells tends to increase. Eliminating this buffering space, or otherwise reducing its ratio, may provide a greater volume of storage in the same physical space.
These issues of read vs. write currents, robustness of conductors and power supplies, reduction in size increasing coercivity and resulting in a correspondingly greater magnetic field, and current design of the magnetic memory cells also carry over into the design and use of magnetic field sensors. Magnetic field sensors are commonly used in hard drive read cells and read heads. In such implementation, the data layer 103 is termed a sense layer. Whereas the orientation M1 of a data layer in an MRAM cell is generally established by a magnetic field provided by the row and column conductors, the orientation M1 of a sense layer in a read head is generally established by a magnetic field emanating from a storage bit proximate to the read head.
Hence, there is a need for an ultra-high density magnetic memory which overcomes one or more of the drawbacks identified above.